PRIDE

Several trends call for a paradigm shift in computing technologies to cope with the performance needs in the future. First, Moore’s Law, which has provided an exponential performance growth by offering a doubling of the number of transistors on a chip biannually, is losing steam. Second, the application landscape of computing is shifting from being compute to becoming data intensive. We believe the time is ripe for a complete departure from the ”von-Neumann bottleneck” contemporary computers suffer from to radically new principles in which compute units are embedded in memory devices - the Processing- In(or near)-Memory paradigm – PIM. PRIDE’s vision is a massively parallel compute chip using 3D integration to extend the runway of silicon technology and making PIM devices in a massively parallel chip a key computing device. In today’s technology, such a chip would offer 1 TFLOPS and a gigantic on- chip memory capacity and bandwidth of 240 GB and 4 TB/s, respectively. To realize this unprecedented performance level, a major challenge is how to translate the enormous bandwidth into performance by managing parallelism and memory locality in an energy-efficient manner. PRIDE will develop principles for accelerator and memory systems for such a massively parallel PIM-based chip and expose it to programmers through a data-centric programming model.

• Programming Models and Runtime Systems Support

• PIMlet accelerators

• Replication and Migration of Data

• Demonstrator